1. Field of the Invention
The present invention relates to a system for efficiently testing ICs (integrated circuits).
2. Description of the Related Art
Conventionally, a burn-in test condition is determined from the viewpoint of ensuring the reliability of ICs for a predetermined period of time. This condition remains the same for both poor-quality ICs which are susceptible to failure and high-quality ICs which are less susceptible to failure.
In general, defective products cannot be completely removed even with a screening test such as a burn-in test. For this reason, the word "predicted failure rate" has been used.
The predicted failure rate is a ratio of defective IC chips predicted to be produced within a predetermined period of time to a plurality of IC chips on one base member (e.g., a wafer) on which a screen test has been conducted.
This predicted failure rate is determined to be a minimum constant value.
A test system including an existing burn-in test is designed such that even the failure rate of poorest-quality products do not exceed a predicted failure rate.
In a conventional test system, however, in order to improve the overall quality level of products, screening tests on all products are conducted under the same condition. Therefore, a screening test is conducted on high-quality IC chips under the same condition as that for poor-quality IC chips.
The purpose of a screening test is to remove defective products, but the test itself produces no value to be added. Therefore, the cost for a screening test must be minimized.
Currently, however, the ratio of the cost of a test step to the total cost of the manufacture of ICs has been greatly increased.
Consider, for example, a DRAM as a typical IC product. The test time increases by 10 times for each new generation (with an increase in degree of integration). That is, the test time for a 4-Mbyte DRAM is 10 times that for a 1-Mbyte DRAM. Therefore, in order to ensure the same production of 4-Mbyte DRAMs as that of 1-Mbyte DRAMs, the production facilities for 4-Mbytes DRAMs need to be 10 times as large as those for 1-Mbyte DRAMs.
In short, the screening test cost of 4-Mbyte DRAMs is 10 times or more that of 1-Mbyte DRAMs.
In practice, the memory size of a 4-Mbyte DRAM is four times that of a 1-Mbyte DRAM. It is, therefore, required that the cost of 4-Mbyte DRAMs be four times or less that of 1-Mbyte DRAMs.
Under the circumstances, rationalization must be achieved to reduce the cost of 4-Mbyte DRAMs to four times or less that of 1-Mbyte DRAMs.
According to a rationalization means currently employed, four IC chips are simultaneously tested. An improvement in efficiency achieved by this rationalization is estimated to be 1.5 times in spite of the fact that the number of products simultaneously tested is two times. Therefore, such a rationalization means is not proper.
As described above, as ICs decrease in size and increase in capacity, the ratio of the cost of a test step to the total cost for the manufacture of ICs inevitably increases. Therefore, demands have arisen for some novel rationalization for suppressing the cost of a test step.